The present invention relates to a microcontroller and a method of controlling the same.
In recent years, there has been an increasing demand to reduce power consumption in electronic devices. For example, in a microcontroller that mounts a UART communication function, as shown in an operation timing chart in FIG. 22, a chip state must be constantly set to RUN to receive UART data that is supplied at arbitrary timings. In short, a clock supply to a UART data receiving unit for receiving data and to a CPU to process the received data is constantly required. As a result, high electric power is consumed regardless of whether to receive the UART data.
An example to solve such a problem is a technique as disclosed in Japanese Unexamined Patent Application Publication No. 2007-58347. FIG. 23 is a block diagram of a reception system 1 of UART data disclosed in Japanese Unexamined Patent Application Publication No. 2007-58347. As shown in FIG. 23, the reception system 1 includes a data reception unit 2, a clock signal supply control means 3, an oscillator 4, an interruption control unit 5, and a CPU 6. The data reception unit 2 includes a FIFO memory 7.
Upon detection of a start bit of a reception signal during HALT (power saving period), the data reception unit 2 starts data reception of the UART data. Further, upon detecting the start bit, the data reception unit 2 supplies a start request signal to the clock signal supply control means 3, and an interruption signal to the interruption control unit 5. Accordingly, a clock signal is supplied to the interruption control unit 5 and the CPU 6, thereby the interruption control unit 5 and the CPU 6 start the operations.
Since the oscillator 4 does not stop even in the HALT period, the data reception unit 2 operates according to the clock signal through the clock signal supply control means 3. The data reception unit 2 stores, in the FIFO memory 7, the UART data that is received upon receiving the clock signal as the operation clock.
Upon receiving the start request signal from the data reception unit 2, the clock signal supply control means 3 supplies the clock signal to the interruption control unit 5 and the CPU 6.
Upon receiving the interruption signal from the data reception unit 2, the interruption control unit 5 performs arbitration with an interruption signal supplied from another peripheral circuit, and then outputs the interruption signal to the CPU 6.
When the clock supply is re-started, the CPU 6 reads out all the data in the FIFO memory 7 of the data reception unit 2. Then, the CPU 6 directly reads out the UART data in a reception buffer of the data reception unit 2. According to such an operation, the CPU 6 is able to process all the UART data received by the reception system 1.
FIG. 24 shows a flow chart for describing an operation of the reception system 1. First, in HALT (power saving period) (YES in S1), the clock signal is supplied to the data reception unit 2, and the supply of the clock signal to the CPU 6 is stopped (S2). When the data reception unit 2 starts receiving the UART data, the start request signal is transmitted to the clock signal supply control means 3 (YES in S3), and the clock signal is supplied to the CPU 6 (S4).
FIG. 25 shows an operation timing chart of the reception system 1. As shown in FIG. 25, before time t1, the state of the chip in which the reception system 1 is formed is HALT. In this state, the clock signal is not supplied to the interruption control unit 5 and the CPU 6, and the power consumption is reduced compared with the case in which the normal operation is performed as shown in FIG. 22.
At time t1, when the UART data is received, the clock signal is supplied to the interruption control unit 5 and the CPU 6, and the interruption control unit 5 and the CPU 6 start operations. Accordingly, the chip state becomes the RUN state.
After time t2 in which the UART data is not transmitted, the chip state becomes HALT. In this state, as is similar to time before time t1, the clock signal is not supplied to the interruption control unit 5 and the CPU 6, thereby reducing the power consumption.
Other related arts include Japanese Unexamined Patent Application Publication Nos. 2004-246793, 5-342435, and 2003-186863. Japanese Unexamined Patent Application Publication No. 2004-246793 discloses a technique in which an oscillation controller controls a crystal oscillator by an oscillation enable signal, and the crystal oscillator stops when the oscillation enable signal becomes a low level. Further, Japanese Unexamined Patent Application Publication No. 5-342435 discloses a technique in which the UART transmits a re-transmission request signal when a parity error is detected, thereafter the UART stops the operation, and the UART signal becomes the low level, which indicates a wait state. Further, Japanese Unexamined Patent Application Publication No. 2003-186863 discloses a technique to judge an input of a reception input signal different from any basic pattern before detecting reception completion by counting a predetermined number of bits as abnormal.